This invention relates generally to digital to analog converters (DACs), and more particularly the invention relates to a DAC having a sub-ranging voltage output with increased multiplying bandwidth and reduced power.
There is a growing demand f or small multichannel, medium resolution high bandwidth low power DACS. Many applications such as robotic, automatic test equipment, monitors, work stations, copiers, cameras, portable equipment, scanners., video, graphic systems and others require high-multiplying bandwidth multiple channel DACs implemented efficiently and cost effectively. Such applications require elements for controlling, adjusting and tuning fast signals using digitally controlled gain or attenuation.
Segment converters can be arranged in cascaded formats, such that a first stage employing a resistor string decodes the most significant bits and a second stage decodes the remaining lower order bits. A nonlinear converter of the general type is described by Gryzbowski et al. "Nonlinear Functions from D/A converters," Electronic Engineering, 1971, pp 48-51. This converter is designed for operation with relay switching. U.S. Pat. No. 3,997,892 (Susset) discloses a cascaded nonlinear converter design intended for use with low speed semiconductor switching where a DC signal is applied across the positive and negative terminals of the reference input. In this design both the first and second stages comprise a resistor string segment type converter. The converter design includes buffer amplifiers to prevent the second stage resistor string (LSB DAC) from loading the first stage resistor string. The architecture is slow, takes much area, and places many different types of devices in series with the signal path which makes it impractical for multichannel and high multiplying bandwidth applications.
U.S. Pat. Nos. 4,338,591 and No. 4,491,852 (Tuthill) disclose a two-stage cascaded converter intended for high resolution, low speed applications wherein the first stage comprises a series connected resistor string segment converter. The voltage across the selected resistor of the string is, in turn, coupled through a pair of buffer amplifiers to the input terminals of a conventional second stage inverted R-2R LSB DAC. The DAC uses buffer amplifiers for precision reasons. The architecture is slow, takes much area, places many different types of devices in series with the signal path which makes it impractical for multichannel and high multiplying bandwidth applications.
Another type of DAC disclosed in the prior art for multiple channels of DC (constant reference) type DACS, uses a single DAC whose output feeds multiple sample and hold amplifiers. This implementation gives excellent matching between channels but requires a systematic updating and refreshing of each channel which causes glitches in the DAC outputs and creates a noisy analog environment for the system designer.
Although the prior art converters noted above embody certain attractive aspects, they are not capable of the high speed, low distortion, low power, low noise, small size, and multiple channels now required in many applications.